The scaling of very large scale integration (VLSI) circuits is an ongoing effort. With circuits becoming smaller and smaller, device driving current becomes more important. Device current is closely related to gate length, gate capacitance, and carrier mobility. Shortening poly-gate length, increasing gate capacitance, and increasing carrier mobility can improve the device's current performance. Gate length reduction is an effort in order to shrink circuit size. Increasing gate capacitance has also been achieved by efforts such as reducing gate dielectric thickness, increasing gate dielectric constant, and the like. In order to further improve device current, enhancing carrier mobility has also been explored.
Among efforts made to enhance carrier mobility, forming a strained silicon channel is a known practice. Strain, also referred to as stress, can enhance bulk electron and hole mobility. The performance of a metal-oxide-semiconductor (MOS) device can be enhanced through a strained-surface channel. This technique allows performance to be improved at a constant gate length, without adding complexity to circuit fabrication or design.
When silicon (Si) is placed under strain, the in-plane, room temperature electron mobility is dramatically increased. One way to develop strain is by using a graded SiGe epitaxy layer as a substrate on which a layer of relaxed SiGe is formed. A layer of Si is formed on the relaxed Si layer. MOS devices are then formed on the silicon layer, which has inherent strain. Since the lattice constant of SiGe is greater than that of Si, the Si film is under biaxial tension and thus the carriers exhibit strain-enhanced mobility.
Strain in a device may have components in three directions; parallel to the MOS device channel length, parallel to the device channel width, and perpendicular to the channel plane. The strains parallel to the device channel length and width are called in-plane strains. Research has revealed that bi-axial, in-plane tensile strain field can improve nMOS performance, and compressive strain parallel to channel length direction can improve pMOS device performance.
Strain can also be applied by forming a strained topside or passivation film of a dielectric material (e.g., silicon nitride film) over underlying layers containing the integrated structure, such as a MOS device. This film, in addition to functioning as an insulation film, acts to protect the underlying structure from moisture and ion contamination that can damage or destroy the structure by causing corrosion and electrical shorts. When a passivation film is deposited on a MOS device, due to the lattice spacing mismatch between the passivation film and the underlying MOS device, an in-plane strain develops to match the lattice spacing. However, what is needed is a method to impose strain more proximate the channel region, thus increasing the imparted strain, without adding much complexity into the manufacturing process.